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The European Project Creating Extensible, Energy-Efficient RISC-V CPUs

Some European researchers are developing open-source RISC-V cores to compete with x86 and Arm, and are relying on only €8 million in funding.

Details about the ambitious eProcessor project were shared at the International Supercomputing Conference (ISC) in Hamburg, Germany, last month. The conference is a showcase for pan-European high-performance computing projects.

The project’s goal is to develop building blocks – including single-core and multi-core RISC-V cores – for European organizations building basic computing devices or high-performance systems. The researchers are developing other modules, such as AI cores, that can be tacked on to RISC-V CPUs.

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The researchers are topping off the chip designs with a complete open-source software stack, including the OS. System builders will get a full stack of offerings to build RISC-V systems while keeping the cost minimal.

Many researchers are building RISC-V cores, but the eProcessor is ambitious in scope. It is operating on funding of €8 million, with €4 million from the EU. It is similar to work being done by fabless chip designers developing both the hardware and software, but it doesn’t use cutting-edge memory and throughput technologies.

e-Processor poster presented at ISC 2023 (click here for full view.)

This project is an ambitious combination of processor design, based on the RISC-V open-source hardware ISA, applications, and system software extending pre-existing intellectual property, combined with new IP that can be used as building blocks for future HPC systems, both for traditional and emerging application domains.

 The Researchers wrote in a poster presented at ISC

One of the project’s goals is to “advance the state-of-the-art for the ML accelerators by developing arithmetic units to support simultaneously a wide range of reduced and mixed precision (1, 2, 4, 8-bit) as well as explore new formats (8- and 16-bit bfloat) for reduced precision floating-point for ML training.”

The project’s final delivery date is 2024, and relies on the low-cost characteristics of RISC-V, which is a free-to-license instruction set architecture. The “e” in eProcessor stands for extensible and energy efficient.

RISC-V is a modular architecture with a base of less than 100 instructions. Custom cores, such as AI accelerators or FPGAs, can be tacked on the base ISA like Lego blocks. eProcessor is creating the CPUs, the accelerator modules, and interfaces.

The modular RISC-V design is seen as a strength compared to commercial chip rivals relying on integration. Companies can make custom chips by selecting only necessary accelerators, instead of relying on megachips with unneeded processing cores.

There are mixed views on integrated chips for supercomputing. AMD has integrated the CPU and the GPU into its MI300A silicon (the engine of the upcoming U.S. El Capitan supercomputer), but Intel has pulled back on plans to integrate the CPU and GPU into a supercomputing chip, and will keep its supercomputing GPU products discrete.

The first eProcessor tapeout, planned for August, will be a single-core chip, targeted at edge devices and microservers. The multicore chip (dual- or quad-core), which is for high-performance computing devices, is slated to be taped out by the end of the project in 2024.

We will not only implement the core, we will provide the full stack. We will port the operating system to it, some network and applications, in order to evaluate it with real-world applications, not just benchmarks.

Project dissemination lead Yannis Papaefstathiou told HPCwire

And all of it will be open for non-commercial use,” he added. “Not all of it will be open-source – there will be components both hardware and software that will be open source – but we want to be open to anyone for non-commerical use.”

The design itself doesn’t include features found in the newer Intel, AMD, and Arm chips. The designers are targeting up to 2GHz frequency and DDR4 memory on GlobalFoundries’ 22nm process.

The researchers are developing 64-bit single-core and multicore out-of-order processors and adaptive caches. The AI accelerators are focused on mixed-precision vector calculations.

But the intent of eProcessor is obvious – it is a chip for those that want something low-tech and low-cost.

eProcessor is part of the EuroHPC project, and involves many companies and universities. It is one among many RISC-V developments across Europe.  One partner, Barcelona Supercomputing Centre, is focusing on vector calculations and the HPC side of the chip. French company Cortus is handling a part of the processor core design. Other participants include the University of Rome, the University of Bielefeld, and companies Thales, Exapsys, Chalmers, and Extoll.

Beyond eProcessor, there are many fragmented initiatives across Europe to develop RISC-V chips. The Barcelona Supercomputing is making RISC-V CPUs, and the European Processor Initiative (EPI) is developing a high-performance accelerator, called EPAC, which has vector processors. The EU is opening up funding to the tune of €270 million to make RISC-V hardware and software. eProcessor is using EPI IP such as vector accelerator and L2 cache.

Another interesting RISC-V project in Europe presented at ISC is called ExCALIBUR, which is a collection of diverse RISC-V boards and software that is accessible to customers to test applications. The testbed offers the best-of RISC-V, including physical chips from the likes of Alibaba and SiFive, and soft cores which can be tested on FPGAs. Users can apply for access via the project’s website, which is hosted by the University of Edinburgh.

ExCALIBUR poster presented at ISC 2023. Click here for full view.

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