3D Inspection Solutions

Dual use PHY for chiplet and chip scale packaging

The UniPHY dual-use chiplet PHY developed by YorChip in Silicon Valley covers a wide range of electrostatic discharge (ESD) voltages from 50V to 250V to support the different types of packages.

The company is using proven partner IP and the UniPHY die-to-die technology to deliver off-the-shelf, low cost, secure chiplets at scale alongside a complete ecosystem of off the shelf chiplets. 

The key invention here is simultaneously supporting the spectrum of ESD standards for chiplets in die form (50V) and traditional packages (250V)

3D Inspection Solutions | Koh Young America

Ahmad Tavakoli, VP Analog of YorChip

While maintaining ultra-low power of chiplets over traditional I/O such as LVDS/GPIO. Packaged chiplets are suitable for customers seeking fast time to market, more robust markets and low cost solutions.

Ahmad Tavakoli

Early customers are already designing with UniPHY and finished chiplets will sample in Q3 2024 with volume production in early 2025.

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The chiplet market is expected to reach more than US$47 Billion by 2031, representing one of the fastest growing segments of the semiconductor industry at more than 40% CAGR from 2021 to 2031. This growth is expected to be enabled by the considerable cost reduction and improved yields chiplets will enable as compared to traditional system-on-chip (SoC) designs.

However chiplets have been limited to High Performance Computing environments using the most advanced technology nodes with per unit device costs in the tens to hundreds of dollars. Lead-time and NRE cost to develop the custom substrate, chiplet package and system level test can easily exceed $500,000 and take more than six months.

Instead the UniPHY approach enables lower costs with the flexibility of packaged chiplets. This accelerates the design cycle to a few weeks and reduces costs by more than 80%.

Applied Materials pushes chiplet tech
Siemens EDA teams for 3D and chiplet designs

The chiplet market is expected to reach more than US$47 Billion by 2031, representing one of the fastest growing segments of the semiconductor industry at more than 40% CAGR from 2021 to 2031. This growth is expected to be enabled by the considerable cost reduction and improved yields chiplets will enable as compared to traditional system-on-chip (SoC) designs.

However chiplets have been limited to High Performance Computing environments using the most advanced technology nodes with per unit device costs in the tens to hundreds of dollars. Lead-time and NRE cost to develop the custom substrate, chiplet package and system level test can easily exceed $500,000 and take more than six months.

Instead the UniPHY approach enables lower costs with the flexibility of packaged chiplets. This accelerates the design cycle to a few weeks and reduces costs by more than 80%.

Applied Materials pushes chiplet tech
Siemens EDA teams for 3D and chiplet designs

We are excited to announce the first dual-use chiplet PHY

Kash Johal, CEO of YorChip

Our mission is enabling chiplets for mass markets, and this patent-pending technology will be key to unlocking pervasive use of chiplets in mass markets for all customers, small, medium and large.

Kash Johal

www.yorchip.com

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